1. Field of the Invention
The present invention is directed to bus architectures for System-on-a-Chip (SoC) devices, and more particularly to a clock domain crossing interface for transferring a synchronous clock signal from one clock domain to another clock domain in a SoC device.
2. Description of the Related Art
The term “system-on-a-chip” or SoC commonly refers to an integrated circuit on which all of the necessary electronic circuits and parts are packaged to create a complete “system” (e.g. a hand-held or vehicle-mounted computer, cell phone, digital camera, etc.). Such circuits normally include a microcontroller or microprocessor, memory, timing sources, peripherals and external interfaces to analog and/or digital devices. These components are interconnected by a plurality of busses, such as those defined in the Advanced Microcontroller Bus Architecture (AMBA), developed by ARM Ltd. AMBA defines specifications for the busses used in SoC designs, and includes an Advanced System Bus (ASB), a High-performance Bus (AHB), Advanced Peripheral Bus (APB) and, more recently, an Advanced eXtensible Interface (AXI).
SoC development involves comprehensive and integrated design, verification, and application development phases before a design is committed to silicon. Design methodologies have traditionally focused on partition-based implementation and verification where the partitions are based on clock domains. A clock domain is defined as that part of the design driven by either a single clock or clocks that have constant phase relationships. Domains that have clocks with different phase and time relationships are considered to be different clock domains. Typical SoC devices include multiple interfaces operating at different clock frequencies, resulting in multiple asynchronous clock domains across which signals must pass.
A clock domain crossing (CDC) occurs when a signal crosses from one clock domain into another. Interfaces have been developed to facilitate such domain crossings. These interfaces must conform to strict design principles for reliable operation, which poses challenges in terms of verification. Since there is no constant phase and time relationship between different clock domains, a condition known as ‘metastability’ can occur if a signal is not asserted long enough to be registered such that the signal appears asynchronous on the incoming clock boundary.
It is known in the art to synchronize a signal that crosses from a lower clocked domain to a higher clocked domain by registering the signal through a flip-flop that is clocked by the lower frequency source clock domain, thereby holding the signal long enough to be detected by the higher frequency destination clock domain. However, synchronizing a signal that traverses from a higher frequency clock domain to a lower frequency clock domain typically requires a register in each clock domain with a feedback path from the destination domain to the source domain for confirming signal detection. For a discussion of these prior art approaches and the challenges of metastability in CDC design and verification, see Clock Domain Crossing: Closing the Loop on Clock Domain Functional Implementation Problems, Cadence Design Systems, Inc., 2004; and Narain, P. and Cummings, C, Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification, SNUG Boston 2008.